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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
Copyright (c) 2000, Power Innovations Limited, UK MARCH 1999 - REVISED MARCH 2000
TELECOMMUNICATION SYSTEM 2x100 A 10/1000 OVERVOLTAGE PROTECTORS
G
Ion-Implanted Breakdown Region - Precise DC and Dynamic Voltages
DEVICE `7070 `7080 `7095 `7125 `7135 `7145 `7180 `7210 `7250 `7290 `7350 `7400 VDRM V 58 65 75 100 110 120 145 160 200 230 275 300 V(BO) V 70 80 95 125 135 145 180 210 250 290 350 400
SL PACKAGE (TOP VIEW)
T G R
1 2 3 MDXXAGA
device symbol
T R
G
Rated for International Surge Wave Shapes - Single and Simultaneous Impulses
SD7XAB
WAVE SHAPE 2/10 s 8/20 s 10/160 s 10/700 s 10/560 s 10/1000 s
STANDARD GR-1089-CORE IEC 61000-4-5 FCC Part 68 FCC Part 68 ITU-T K20/21 FCC Part 68 GR-1089-CORE
ITSP A 500 350 250 200 130 100
G Terminals T, R and G correspond to the alternative line designators of A, B and C
G
3-Pin Through-Hole Packaging - Compatible with TO-220AB pin-out - Low Height. . . . . . . . . . . . . . . . . . . . .8.3 mm
description
The TISP7xxxH3SL limits overvoltages between the telephone line Ring and Tip conductors and Ground. Overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone line. Each terminal pair, T-G, R-G and T-R, has a symmetrical voltage-triggered bidirectional thyristor protection characteristic. Overvoltages are initially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. This low-voltage on state causes the current resulting from the overvoltage to be safely diverted through the device. The high crowbar holding current prevents d.c. latchup as the diverted current subsides. This TISP7xxxH3SL range consists of twelve voltage variants to meet various maximum system voltage levels (58 V to 300 V). They are guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. These high current protection devices are in a 3-pin single-in-line (SL) plastic package and are supplied in tube pack. For alternative impulse rating, voltage and holding current values in SL packaged protectors, consult the factory. For lower rated impulse currents in the SL package, the 45 A 10/1000 TISP7xxxF3SL series is available. These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise and matched breakover control and are virtually transparent to the system in normal operation
PRODUCT
INFORMATION
Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters.
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
absolute maximum ratings, TA = 25C (unless otherwise noted)
RATING `7070 `7080 `7095 `7125 `7135 Repetitive peak off-state voltage, (see Note 1) `7145 `7180 `7210 `7250 `7290 `7350 `7400 Non-repetitive peak on-state pulse current (see Notes 2, and 3) 2/10 (Telcordia GR-1089-CORE, 2/10 voltage wave shape) 8/20 s (IEC 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 10/160 s (FCC Part 68, 10/160 s voltage wave shape) 4/250 (ITU-T K.20/21, 10/700 voltage wave shape, dual) 0.2/310 (CNET I 31-24, 0.5/700 voltage wave shape) 5/310 (ITU-T K.20/21, 10/700 voltage wave shape, single) 5/320 s (FCC Part 68, 9/720 s voltage wave shape) 10/560 s (FCC Part 68, 10/560 s voltage wave shape) 10/1000 (Telcordia GR-1089-CORE, 10/1000 voltage wave shape) Non-repetitive peak on-state current (see Notes 2, 3 and 4) 20 ms (50 Hz) full sine wave 16.7 ms (60 Hz) full sine wave 1000 s 50 Hz/60 Hz a.c. Initial rate of rise of on-state current, Junction temperature Storage temperature range Exponential current ramp, Maximum ramp value < 200 A diT/dt TJ Tstg ITSM 55 60 0.9 400 -40 to +150 -65 to +150 A/s C C A ITSP 500 350 250 225 200 200 200 130 100 A VDRM SYMBOL VALUE 58 65 75 100 110 120 145 160 200 230 275 300 V UNIT
NOTES: 1. Derate value at -0.13%/C for temperatures below 25 C. 2. Initially the TISP7xxxH3 must be in thermal equilibrium. 3. These non-repetitive rated currents are peak values of either polarity. The rated current values may be applied to any terminal pair. Additionally, both R and T terminals may have their rated current values applied simultaneously (in this case the G terminal return current will be the sum of the currents applied to the R and T terminals). The surge may be repeated after the TISP7xxxH3 returns to its initial conditions. 4. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track widths. Derate current values at -0.61 %/C for ambient temperatures above 25 C
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
electrical characteristics for any terminal pair, TA = 25C (unless otherwise noted)
PARAMETER IDRM Repetitive peak offstate current V D = VDRM TEST CONDITIONS TA = 25C TA = 85C `7070 `7080 `7095 `7125 `7135 V(BO) Breakover voltage dv/dt = 750 V/ms, R SOURCE = 300 `7145 `7180 `7210 `7250 `7290 `7350 `7400 `7070 `7080 `7095 `7125 dv/dt 1000 V/s, Linear voltage ramp, V(BO) Impulse breakover voltage Maximum ramp value = 500 V di/dt = 20 A/s, Linear current ramp, Maximum ramp value = 10 A `7135 `7145 `7180 `7210 `7250 `7290 `7350 `7400 I(BO) VT IH dv/dt ID Breakover current On-state voltage Holding current Critical rate of rise of off-state voltage Off-state current dv/dt = 750 V/ms, R SOURCE = 300 IT = 5 A, tW = 100 s IT = 5 A, di/dt = +/-30 mA/ms Linear voltage ramp, Maximum ramp value < 0.85V DRM VD = 50 V f = 1 MHz, V d = 1 V rms, VD = 0, TA = 85C `7070 thru `7095 `7125 thru `7210 `7250 thru `7400 f = 1 MHz, Vd = 1 V rms, VD = -1 V `7070 thru `7095 `7125 thru `7210 `7250 thru `7400 Coff Off-state capacitance f = 1 MHz, Vd = 1 V rms, VD = -2 V `7070 thru `7095 `7125 thru `7210 `7250 thru `7400 f = 1 MHz, Vd = 1 V rms, VD = -50 V `7070 thru `7095 `7125 thru `7210 `7250 thru `7400 f = 1 MHz, (see Note 5) NOTE 5: To avoid possible voltage clipping, the `7125 is tested with VD = -98 V. Vd = 1 V rms, VD = -100 V `7125 thru `7210 `7250 thru `7400 0.15 5 10 170 90 84 150 79 67 140 74 62 73 35 28 33 26 pF 0.1 MIN TYP MAX 5 10 70 80 95 125 135 145 180 210 250 290 350 400 78 88 103 134 144 154 189 220 261 302 362 414 0.8 5 0.6 A V A kV/s A V V UNIT A
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
thermal characteristics
PARAMETER RJA TEST CONDITIONS EIA/JESD51-3 PCB, IT = ITSM(1000), TA = 25 C, (see Note 6) MIN TYP MAX 50 UNIT C/W
Junction to free air thermal resistance
NOTE
6: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
PRODUCT
INFORMATION
4
TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
+i ITSP Quadrant I Switching Characteristic
ITSM IT VT IH V(BO) I(BO)
-v IDRM
VDRM
VD
ID ID VD VDRM
IDRM +v
I(BO) V(BO)
IH VT IT ITSM
Quadrant III Switching Characteristic ITSP -i V D = 50 V and ID = 10 A used for reliability release
PM4XAAC
Figure 1. VOLTAGE-CURRENT CHARACTERISTIC FOR TERMINAL PAIRS
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
TYPICAL CHARACTERISTICS
OFF-STATE CURRENT vs JUNCTION TEMPERATURE
10 VD = +50 V
Normalised Breakover Voltage
TC7AAA
1.10
NORMALISED BREAKOVER VOLTAGE vs JUNCTION TEMPERATURE TC7AAB
'7125 THRU '7210 '7250 THRU '7400
1 |ID| - Off-State Current - A
0*1
VD = -50 V
1.05
'7070 THRU '7095 '7250 THRU '7400 1.00
0*01
0*001
0*0001 0 25 50 75 100 125 TJ - Junction Temperature - C 150
0.95 -25 0 25 50 75 100 125 TJ - Junction Temperature - C 150
Figure 2.
Figure 3.
IT On-State Current - Holding Current Breakover Current -Normalised to 25 C A
200 4.0 150 TA = 25 C 70 50 40 2.0 30
1.5 20 15
NORMALISED BREAKOVER CURRENT ON-STATE CURRENT vs vs ON-STATE VOLTAGE JUNCTION TEMPERATURE TC7AAD
+ I(BO), - I(BO) '7070 THRU '7210
2.0
NORMALISED HOLDING CURRENT vs JUNCTION TEMPERATURE TC7AAC
3.0 100 tW = 100 s
1.5 Normalised Holding Current
1.0 0.9 0.8 0.7 0.6 0.5 0.4
10 1.0 7 0.9 5 0.8 4 0.7 3 0.6 2 0.5 1.5
'3125 THRU '3210
+ I(BO), - I(BO) '7250 THRU '7400
'3250 THRU '3350
'3070 THRU '3095 5 0 1.5 252 50 3 754 100 7 125 - On-State Voltage - V TJV-T Junction Temperature - C 10 150
1 0.4 0.7 -251
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - C
Figure 4.
Figure 5.
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
TYPICAL CHARACTERISTICS
NORMALISED CAPACITANCE vs OFF-STATE VOLTAGE
TJ = 25C Vd = 1 Vrms
'7070 '7080 '7095
'7125 '7135 '7145 '7180 '7210
'7250
'7290
Capacitance Normalised to VD = -1V
0.8 0.7 0.6 0.5 '7070 THRU '7095 0.4
C - Differential Off-State Capacitance - pF
0.9
75 70 65
55 50 45 40 35 30 50 60 70 80
'7125 THRU '7210 0.3 '7250 THRU '7400
0.2 1 2 3 5 10 20 30 50 100 150 VD - Off-state Voltage - V
100
VDRM - Repetitive Peak Off-State Voltage - V
Figure 6.
Figure 7.
PRODUCT
INFORMATION
60
C = Coff(-2 V) - Coff(-50 V)
150
200 250 300
'7350 '7400
400
TC7AAH
1
TC7AAI
DIFFERENTIAL OFF-STATE CAPACITANCE vs RATED REPETITIVE PEAK OFF-STATE VOLTAGE
80
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
RATING AND THERMAL INFORMATION
NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION
30 ITSM(t) - Non-Repetitive Peak On-State Current - A VGEN = 600 V rms, 50/60 Hz 20 15 10 9 8 7 6 5 4 3 2 1.5 1 0.9 0.8 0*1 RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB, TA = 25 C SIMULTANEOUS OPERATION OF R AND T TERMINALS. G TERMINAL CURRENT = 2xITSM(t)
TI7AB
1
10
100
1000
t - Current Duration - s
Figure 8.
VDRM DERATING FACTOR vs MINIMUM AMBIENT TEMPERATURE
1.00 0.99
TI7AC
IMPULSE RATING vs AMBIENT TEMPERATURE
700 600 500 IEC 1.2/50, 8/20 400 Impulse Current - A TELCORDIA 2/10
TC7HAA
0.98 Derating Factor 0.97 0.96
300 250 200 150 120
FCC 10/160 ITU-T 10/700
'7070 THRU '7095
FCC 10/560 TELCORDIA 10/1000
0.95 '7125 THRU '7210 0.94 '7250 THRU '7400 0.93 -40 -35 -30 -25 -20 -15 -10 -5
100 90 80 70 -40 -30 -20 -10 0
0
5
10 15 20 25
10 20 30 40 50 60 70 80
TAMIN - Minimum Ambient Temperature - C
TA - Ambient Temperature - C
Figure 9.
Figure 10.
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
APPLICATIONS INFORMATION deployment
These devices are three terminal overvoltage protectors. They limit the voltage between three points in the circuit. Typically, this would be the two line conductors and protective ground (Figure 11).
Th3 Th1 Th2
Figure 11. MULTI-POINT PROTECTION
In Figure 11, protectors Th2 and Th3 limit the maximum voltage between each conductor and ground to the V(BO) of the individual protector. Protector Th1 limits the maximum voltage between the two conductors to its V(BO) value. Manufacturers are being increasingly required to design in protection coordination. This means that each protector is operated at its design level and currents are diverted through the appropriate protector e.g. the primary level current through the primary protector and lower levels of current may be diverted through the secondary or inherent equipment protection. Without coordination, primary level currents could pass through the equipment only designed to pass secondary level currents. To ensure coordination happens with fixed voltage protectors, some resistance is normally used between the primary and secondary protection. The values given in this data sheet apply to a 400 V (d.c. sparkover) gas discharge tube primary protector and the appropriate test voltage when the equipment is tested with a primary protector.
impulse testing
To verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various impulse wave forms. The table below shows some common values.
PEAK VOLTAGE STANDARD SETTING V GR-1089-CORE 2500 1000 1500 FCC Part 68 (March 1998) 800 1000 1500 1500 I 31-24 1500 1000 ITU-T K20/K21 1500 4000 4000 VOLTAGE WAVE FORM s 2/10 10/1000 10/160 10/560 9/720 (SINGLE) (DUAL) 0.5/700 10/700 (SINGLE) (SINGLE) (DUAL) PEAK CURRENT VALUE A 500 100 200 100 25 37.5 2 x 27 37.5 25 37.5 100 2 x 72 CURRENT s 2/10 10/1000 10/160 10/560 5/320 5/320 4/250 0.2/310 5/310 5/310 5/310 4/250 TISP7xxxH3 A 500 100 250 130 200 200 2 x 225 200 200 200 200 2 x 225 0 0 NA NA NA 4.5 6.0 0 NA SERIES COORDINATION RESISTANCE
WAVE FORM 25 C RATING RESISTANCE
0
(MIN).
NA
FCC Part 68 terminology for the waveforms produced by the ITU-T recommendation K21 10/700 impulse generator NA = Not Applicable, primary protection removed or not specified.
PRODUCT
INFORMATION
9
TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
If the impulse generator current exceeds the protectors current rating then a series resistance can be used to reduce the current to the protectors rated value and so prevent possible failure. The required value of series resistance for a given waveform is given by the following calculations. First, the minimum total circuit impedance is found by dividing the impulse generators peak voltage by the protectors rated current. The impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then subtracted from the minimum total circuit impedance to give the required value of series resistance. In some cases the equipment will require verification over a temperature range. By using the rated waveform values from Figure 10, the appropriate series resistor value can be calculated for ambient temperatures in the range of -40 C to 85 C.
a.c. power testing
The protector can withstand the G return currents applied for times not exceeding those shown in Figure 8. Currents that exceed these times must be terminated or reduced to avoid protector failure. Fuses, PTC (Positive Temperature Coefficient) resistors and fusible resistors are overcurrent protection devices which can be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere. In some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. The current versus time characteristic of the overcurrent protector must be below the line shown in Figure 8. In some cases there may be a further time limit imposed by the test standard (e.g. UL 1459 wiring simulator failure).
capacitance
The protector characteristic off-state capacitance values are given for d.c. bias voltage, VD, values of 0, -1 V, -2 V and -50 V. Where possible values are also given for -100 V. Values for other voltages may be calculated by multiplying the VD = 0 capacitance value by the factor given in Figure 6. Up to 10 MHz the capacitance is essentially independent of frequency. Above 10 MHz the effective capacitance is strongly dependent on connection inductance. For example, a printed wiring (PW) trace of 10 cm could create a circuit resonance with the device capacitance in the region of 50 MHz. In many applications, the typical conductor bias voltages will be about -2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 V and the other at -50 V.
normal system voltage levels
The protector should not clip or limit the voltages that occur in normal system operation. For unusual conditions, such as ringing without the line connected, some degree of clipping is permissible. Under this condition, about 10 V of clipping is normally possible without activating the ring trip circuit. Figure 9 allows the calculation of the protector VDRM value at temperatures below 25 C. The calculated value should not be less than the maximum normal system voltages. The TISP3290H3, with a VDRM of 220 V, can be used for the protection of ring generators producing 105 V rms of ring on a battery voltage of -58 V. The peak ring voltage will be 58 + 1.414*105 = 206.5 V. However, this is the open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. For the extreme case of an unconnected line, the temperature at which clipping begins can be calculated using the data from Figure 9. To possibly clip, the VDRM value has to be 206.5 V. This is a reduction of the 220 V 25 C VDRM value by a factor of 206.5/220 = 0.94. Figure 9 shows that a 0.94 reduction will occur at an ambient temperature of -32 C. In this example, the TISP3290H3 will allow normal equipment operation, even on an open-circuit line, provided that the minimum expected ambient temperature does not fall below -32 C.
JESD51 thermal measurement method
To standardise thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard (JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft3) cube which contains the test PCB (Printed Circuit Board) horizontally mounted at the centre. Part 3 of the
PRODUCT
INFORMATION
10
TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. The thermal measurements used the smaller 76.2 mm x 114.3 mm (3.0 " x 4.5 ") PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal resistance) and represent a worse case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance and so can dissipate higher power levels than indicated by the JESD51 values.
PRODUCT
INFORMATION
11
TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
typical circuits
TIP WIRE
F1a Th3 Th1 Th2 F1b
R1a PROTECTED EQUIPMENT E.G. LINE CARD R1b TISP7xxxH3 AI7XBK
RING WIRE
Figure 12. PROTECTION MODULE
R1a Th3 Th1 Th2 R1b TISP7150H3 D.C. AI7XBL SIGNAL
Figure 13. ISDN PROTECTION
OVERCURRENT PROTECTION TIP WIRE R1a COORDINATION RESISTANCE R1b
RING/TEST PROTECTION
TEST RELAY
RING RELAY
SLIC RELAY S3a
SLIC PROTECTION
Th4
Th3 Th1 Th2
S1a
S2a SLIC
Th5 S3b S1b S2b
RING WIRE
TISP7xxxH3
TISP6xxxx, TISPPBLx, 1/2TISP6NTP2 C1 220 nF VBAT
TEST EQUIPMENT
RING GENERATOR
AI7XBJ
Figure 14. LINE CARD RING/TEST PROTECTION
PRODUCT
INFORMATION
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TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
MECHANICAL DATA SL003 3-pin plastic single-in-line package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly.
SL003 9,75 (0.384) 9,25 (0.364) 3,40 (0.134) 3,20 (0.126)
Index Notch
8,31 (0.327) MAX 12,9 (0.492) MAX
6,60 (0.260) 6,10 (0.240)
4,267 (0.168) MIN
1
2
3 2,54 (0.100) Typical (see Note A) 2 Places 0,356 (0.014) 0,203 (0.008)
1,854 (0.073) MAX 0,711 (0.028) 0,559 (0.022) 3 Places
ALL LINEAR DIMENSIONS IN MILLIMETERS AND PARANTHETICALLY IN INCHES
MDXXCEA
NOTES: A. Each pin centreline is located within 0,25 (0.010) of its true longitudinal position. B. Body molding flash of up to 0,15 (0.006) may occur in the package lead plane.
PRODUCT
INFORMATION
13
TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL TISP7250H3SL THRU TISP7400H3SL TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. PI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORISED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.
Copyright (c) 2000, Power Innovations Limited
PRODUCT
INFORMATION
14

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